ARM registers - holding values

ARM architecture  has total 16 registers, each register is of 16 bit .

		Special	Role in the procedure call standard
r15		PC	The Program Counter. The Link Register. The Stack Pointer.
r14		LR
r13		SP
r12		IP	The Intra-Procedure-call scratch register.
r11	v8		Variable-register 8. Variable-register 7.
r10	v7
r9		v6 SB TR	Platform register. The meaning of this register is defined by the platform standard.
r8	v5		Variable-register 5.
r7	v4		Variable register 4. Variable register 3. Variable register 2. Variable register 1.
r6	v3
r5	v2
r4	v1
r3	a4		Argument / scratch register 4. Argument / scratch register 3. Argument / result / scratch register 2. Argument / result / scratch register 1.
r2	a3
r1	a2
r0	a1

ARM registers
ARM has 31 general-purpose 32-bit registers. At any one time, 16 of these registers are visible. The other registers are used to speed up exception processing. All the register specifiers in ARM instructions can address any of the 16 visible registers.
The main bank of 16 registers is used by all unprivileged code. These are the User mode registers. User mode is different from all other modes as it is unprivileged, which means:

• User mode can only switch to another processor mode by generating an exception. The SWI instruction provides this facility from program control.
  
• Memory systems and coprocessors might allow User mode less access to memory and coprocessor functionality than a privileged mode.
  Three of the 16 visible registers have special roles:
  

Stack pointer Link register
Program counter

Software normally uses R13 as a Stack Pointer (SP). R13 is used by the PUSH and POP instructions in T variants, and by the SRS and RFE instructions from ARMv6.
Register 14 is the Link Register (LR). This register holds the address of the next instruction after a Branch and Link (BL or BLX) instruction, which is the instruction used to make a subroutine call. It is also used for return address information on entry to exception modes. At all other times, R14 can be used as a general-purpose register.
Register 15 is the Program Counter (PC). It can be used in most instructions as
a pointer to the instruction which is two instructions after the instruction being executed. In ARM state, all ARM instructions are four bytes long (one 32-bit word) and are always aligned on a word boundary. This means that the bottom two bits of the PC are always zero, and therefore the PC contains only 30 non-constant bits. Two other processor states are supported by some versions of the architecture. Thumb® state is supported on T variants, and Jazelle® state on J variants. The PC can be halfword (16-bit) and byte aligned respectively in these states.

The remaining 13 registers have no special hardware purpose. Their uses are defined purely by software. For more details on registers, refer to Registers on page A2-4.

Introduction to the ARM Architecture

ARM DDI 0100I Copyright © 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. A1-3

Introduction to the ARM Architecture

A1.1.2 Exceptions
ARM supports seven types of exception, and a privileged processing mode for each type. The seven types of exception are:

• reset
  
• attempted execution of an Undefined instruction
  
• software interrupt (SWI) instructions, can be used to make a call to an operating system
  
• Prefetch Abort, an instruction fetch memory abort
  
• Data Abort, a data access memory abort
  
• IRQ, normal interrupt
  
• FIQ, fast interrupt.
  When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for R13 and R14. The fast interrupt mode has additional banked registers for fast interrupt processing.
  When an exception handler is entered, R14 holds the return address for exception processing. This is used to return after the exception is processed and to address the instruction that caused the exception.
  Register 13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without the need to save or restore these registers.
  There is a sixth privileged processing mode, System mode, which uses the User mode registers. This is used to run tasks that require privileged access to memory and/or coprocessors, without limitations on which exceptions can occur during the task.
  In addition to the above, reset shares the same privileged mode as SWIs. For more details on exceptions, refer to Exceptions on page A2-16.
  The exception process
  When an exception occurs, the ARM processor halts execution in a defined manner and begins execution at one of a number of fixed addresses in memory, known as the exception vectors. There is a separate vector location for each exception, including reset. Behavior is defined for normal running systems (see section A2.6) and debug events (see Chapter D3 Coprocessor 14, the Debug Coprocessor)
  An operating system installs a handler on every exception at initialization. Privileged operating system tasks are normally run in System mode to allow exceptions to occur within the operating system without state loss.
  

A1-4

Copyright © 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. ARM DDI 0100I

A1.1.3 Status registers
All processor state other than the general-purpose register contents is held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds:

• four condition code flags (Negative, Zero, Carry and oVerflow).
  
• one sticky (Q) flag (ARMv5 and above only). This encodes whether saturation has occurred in saturated arithmetic instructions, or signed overflow in some specific multiply accumulate instructions.
  
• four GE (Greater than or Equal) flags (ARMv6 and above only). These encode the following conditions separately for each operation in parallel instructions:
  
  • —  whether the results of signed operations were non-negative
    
  • —  whether unsigned operations produced a carry or a borrow.
    
• two interrupt disable bits, one for each type of interrupt (two in ARMv5 and below).
  
• one (A) bit imprecise abort mask (from ARMv6)
  
• five bits that encode the current processor mode.
  
• two bits that encode whether ARM instructions, Thumb instructions, or Jazelle opcodes are being
  executed.
  
• one bit that controls the endianness of load and store operations (ARMv6 and above only).
  Each exception mode also has a Saved Program Status Register (SPSR) which holds the CPSR of the task immediately before the exception occurred. The CPSR and the SPSRs are accessed with special instructions.